US 11,677,000 B2
IC structure including porous semiconductor layer under trench isolations adjacent source/drain regions
Uzma B. Rana, Slingerlands, NY (US); Steven M. Shank, Jericho, VT (US); and Anthony K. Stamper, Burlington, VT (US)
Assigned to GlobalFoundries U.S. Inc., Malta, NY (US)
Filed by GlobalFoundries U.S. Inc., Malta, NY (US)
Filed on Oct. 7, 2021, as Appl. No. 17/450,186.
Prior Publication US 2023/0114096 A1, Apr. 13, 2023
Int. Cl. H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 21/76 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/10 (2006.01); H01Q 1/22 (2006.01)
CPC H01L 29/0653 (2013.01) [H01L 29/0847 (2013.01); H01L 29/1083 (2013.01); H01Q 1/2283 (2013.01)] 14 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) structure, comprising:
an active device over a bulk semiconductor substrate, the active device including a semiconductor layer having a center region, a first end region laterally spaced from the center region by a first trench isolation, a second end region laterally spaced from the center region by a second trench isolation, a gate over the center region, and a source/drain region in each of the first and second end regions; and
an isolation structure around the active device in the bulk semiconductor substrate, the isolation structure including:
a polycrystalline isolation layer under the active device,
a third trench isolation around the active device, and
a porous semiconductor layer between the first trench isolation and the polycrystalline isolation layer and between the second trench isolation and the polycrystalline isolation layer.