US 11,676,968 B2
Coaxial contacts for 3D logic and memory
Lars Liebmann, Mechanicville, NY (US); Jeffrey Smith, Clifton Park, NY (US); Anton J. deVilliers, Clifton Park, NY (US); and Kandabara Tapily, Mechanicville, NY (US)
Assigned to Tokyo Electron Limited, Tokyo (JP)
Filed by Tokyo Electron Limited, Tokyo (JP)
Filed on Jan. 6, 2022, as Appl. No. 17/647,294.
Application 17/647,294 is a division of application No. 16/716,901, filed on Dec. 17, 2019, granted, now 11,251,200.
Claims priority of provisional application 62/851,990, filed on May 23, 2019.
Prior Publication US 2022/0130864 A1, Apr. 28, 2022
Int. Cl. H01L 27/118 (2006.01); H01L 23/522 (2006.01); H01L 27/02 (2006.01); H01L 21/768 (2006.01); H10B 99/00 (2023.01); H10B 10/00 (2023.01); H01L 27/105 (2023.01); H01L 27/11 (2006.01)
CPC H01L 27/11807 (2013.01) [H01L 21/76816 (2013.01); H01L 23/5226 (2013.01); H01L 27/0207 (2013.01); H01L 27/1052 (2013.01); H01L 27/11 (2013.01); H01L 2027/11861 (2013.01); H01L 2027/11866 (2013.01); H01L 2027/11875 (2013.01); H01L 2027/11885 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A method for forming a semiconductor device, comprising:
forming a first opening in a dielectric stack over a substrate, the first opening has a cylinder shape with a first sidewall and a first bottom;
depositing a first conductive layer along the first sidewall of the first opening and a first insulating layer along an inner sidewall of the first conductive layer so that the first conductive layer and the first insulating layer having closed-shape and concentrically arranged, a bottom of the first conductive layer and a bottom of the first insulating layer being positioned on the first bottom of the first opening;
etching the dielectric stack along an inner sidewall of the first insulating layer so as to form a second opening, the second opening extending into the dielectric stack and having a second sidewall and a second bottom, the second sidewall being formed along the inner sidewall of the first insulating layer and further extending into the dielectric stack, the second bottom of the second opening being positioned below the bottoms of the first conductive layer and first insulating layer; and
depositing a second conductive layer along the second sidewall of the second opening and a second insulating layer along an inner sidewall of the second conductive layer, a bottom of the second conductive layer and a bottom of the second insulating layer being positioned on the second bottom of the second opening so that the bottom of the second conductive layer is positioned below the bottom of the first conductive layer to form a staggered configuration.