US 11,676,966 B2
Stacked transistors having device strata with different channel widths
Gilbert W. Dewey, Beaverton, OR (US); Jack T. Kavalieros, Portland, OR (US); Willy Rachmady, Beaverton, OR (US); Cheng-Ying Huang, Portland, OR (US); Matthew V. Metz, Portland, OR (US); Kimin Jun, Portland, OR (US); Patrick Morrow, Portland, OR (US); Aaron D. Lilak, Beaverton, OR (US); Ehren Mannebach, Tigard, OR (US); and Anh Phan, Beaverton, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by INTEL CORPORATION, Santa Clara, CA (US)
Filed on Mar. 15, 2019, as Appl. No. 16/354,960.
Prior Publication US 2020/0295003 A1, Sep. 17, 2020
Int. Cl. H01L 27/092 (2006.01); H01L 29/16 (2006.01); H01L 29/20 (2006.01); H01L 29/06 (2006.01); H01L 29/78 (2006.01); H01L 21/8238 (2006.01); H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01); H01L 29/10 (2006.01)
CPC H01L 27/0924 (2013.01) [H01L 21/823807 (2013.01); H01L 21/823821 (2013.01); H01L 23/3128 (2013.01); H01L 23/5383 (2013.01); H01L 24/17 (2013.01); H01L 25/065 (2013.01); H01L 29/0673 (2013.01); H01L 29/1033 (2013.01); H01L 29/16 (2013.01); H01L 29/20 (2013.01); H01L 29/7851 (2013.01); H01L 2224/0401 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) structure, comprising:
a first device stratum including a first channel material, wherein the first channel material includes a wire;
a second device stratum including a second channel material, wherein the second channel material is above and aligned with the first channel material, and the second channel material includes a fin;
a first gate metal at least partially surrounding the first channel material; and
a second gate metal at least partially surrounding the second channel material;
wherein a width of the first channel material is different from a width of the second channel material and the first gate metal has a different material composition than the second gate metal.