US 11,676,900 B2
Electronic assembly that includes a bridge
Eric J. Li, Chandler, AZ (US); Nitin Deshpande, Chandler, AZ (US); Shawna M. Liff, Scottsdale, AZ (US); Omkar Karhade, Chandler, AZ (US); Amram Eitan, Scottsdale, AZ (US); and Timothy A. Gosselin, Phoenix, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Appl. No. 15/778,398
Filed by Intel Corporation, Santa Clara, CA (US)
PCT Filed Dec. 22, 2015, PCT No. PCT/US2015/067418
§ 371(c)(1), (2) Date May 23, 2018,
PCT Pub. No. WO2017/111950, PCT Pub. Date Jun. 29, 2017.
Prior Publication US 2018/0358296 A1, Dec. 13, 2018
Int. Cl. H01L 25/00 (2006.01); H01L 23/538 (2006.01); H01L 23/48 (2006.01); H01L 25/065 (2023.01); H01L 23/36 (2006.01); H01L 23/13 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/367 (2006.01)
CPC H01L 23/5381 (2013.01) [H01L 21/4853 (2013.01); H01L 21/4871 (2013.01); H01L 23/13 (2013.01); H01L 23/36 (2013.01); H01L 23/48 (2013.01); H01L 23/5385 (2013.01); H01L 23/5386 (2013.01); H01L 25/0655 (2013.01); H01L 25/50 (2013.01); H01L 23/367 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 24/81 (2013.01); H01L 24/92 (2013.01); H01L 2224/0612 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/81191 (2013.01); H01L 2224/81192 (2013.01); H01L 2224/81193 (2013.01); H01L 2224/81203 (2013.01); H01L 2224/92125 (2013.01); H01L 2924/15159 (2013.01)] 12 Claims
OG exemplary drawing
 
1. An electronic assembly, comprising:
a substrate that includes an upper surface;
a cavity in the upper surface of the substrate, the cavity having a bottom and sidewalls in the substrate, wherein a portion of the substrate is continuous around the bottom and sidewalls of the cavity;
a bridge that includes an upper surface;
a conductor below the bridge;
an adhesive that secures the bridge within the cavity, the adhesive directly on the conductor but not in contact with the sidewalls of the cavity, wherein a void is laterally between the adhesive and the sidewalls of the cavity;
a first die that includes a silicon-on-chip electronic device, the first die directly contacting the upper surface of the bridge and directly contacting the upper surface of the substrate; and
a second die directly contacting the upper surface of the bridge and directly contacting the upper surface of the substrate, wherein the bridge electrically connects the first die to the second die.
 
11. An electronic assembly, comprising:
a substrate that includes an upper surface;
a plurality of bridges that each include an upper surface, the plurality of bridges being within at least one cavity in the upper surface of the substrate, wherein an adhesive secures the plurality of bridges within the at least one cavity in the substrate, wherein at least some of the plurality of bridges are embedded within a same cavity of the at least one cavity in the upper surface of the substrate;
a plurality of dice, wherein at least one of the plurality of dice includes a memory module, wherein each of the plurality of dice contacts the upper surface of one of the plurality of bridges and directly contacts the upper surface of the substrate;
wherein the plurality of bridges electrically connects ones of the plurality of dice to others of the plurality of dice.