US 11,676,880 B2
High thermal conductivity vias by additive processing
Benjamin Stassen Cook, Rockwall, TX (US); Archana Venugopal, Dallas, TX (US); Luigi Colombo, Dallas, TX (US); and Robert Reid Doering, Garland, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Nov. 26, 2016, as Appl. No. 15/361,399.
Prior Publication US 2018/0151471 A1, May 31, 2018
Int. Cl. H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 23/367 (2006.01); H01L 23/373 (2006.01); H01L 21/48 (2006.01)
CPC H01L 23/3677 (2013.01) [H01L 21/4882 (2013.01); H01L 23/3731 (2013.01); H01L 23/3733 (2013.01); H01L 23/3736 (2013.01)] 24 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a substrate comprising semiconductor material;
an interconnect region disposed above the substrate, the interconnect region comprising a dielectric layer stack comprising dielectric materials;
a component disposed in the substrate and configured to generate heat when operating; and
a thermal via disposed in the interconnect region and landing on a field oxide region formed in the substrate, wherein the thermal via includes a cohered nanoparticle film which includes primarily nanoparticles, wherein each nanoparticle of a plurality of the nanoparticles is attached directly to an adjacent one of the nanoparticles, wherein the thermal via has a thermal conductivity higher than dielectric materials touching the thermal via.