US 11,676,876 B2
Semiconductor die package with warpage management and process for forming such
Ziyin Lin, Chandler, AZ (US); Elizabeth Nofen, Phoenix, AZ (US); Vipul Mehta, Chandler, AZ (US); and Taylor Gaines, Chandler, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Aug. 30, 2019, as Appl. No. 16/557,891.
Prior Publication US 2021/0066152 A1, Mar. 4, 2021
Int. Cl. H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 23/367 (2006.01); H01L 23/373 (2006.01); H01L 21/67 (2006.01)
CPC H01L 23/3178 (2013.01) [H01L 21/565 (2013.01); H01L 21/67288 (2013.01); H01L 23/367 (2013.01); H01L 23/373 (2013.01)] 26 Claims
OG exemplary drawing
 
1. A device, comprising:
a first die;
a plurality of chiplets above the first die;
a first underfill material beneath the chiplets;
a gap fill material between the chiplets, the gap fill material different from the first underfill material;
an interface region between the first underfill material and the gap fill material; and
a mold material adjacent sides of the chiplets, wherein the gap fill material is different from the mold material.