US 11,676,010 B2
Memory sub-system with a bus to transmit data for a machine learning operation and another bus to transmit host data
Amit Gattani, Granite Bay, CA (US); and Poorna Kale, Folsom, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 14, 2019, as Appl. No. 16/601,392.
Prior Publication US 2021/0110252 A1, Apr. 15, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G05B 13/02 (2006.01); G06F 1/00 (2006.01); G06F 7/00 (2006.01); G06N 3/08 (2023.01); G06F 13/16 (2006.01)
CPC G06N 3/08 (2013.01) [G06F 13/1668 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory component to store host data from a host system in a first memory region and to store a machine learning model and input data in a second memory region, wherein the input data is separate from the host data;
a controller comprising an in-memory logic to perform a machine learning operation by applying the machine learning model to the input data to generate an output data;
a bus to receive additional host data from the host system and to provide the additional host data to the memory component; and
an additional bus to receive machine learning data from the host system and to provide the machine learning data to the in-memory logic that is to perform the machine learning operation.