US 11,675,951 B2
Methods and systems for congestion prediction in logic synthesis using graph neural networks
Amur Ghose, Montreal (CA); Yingxue Zhang, Montreal (CA); and Zhanguang Zhang, Montreal (CA)
Assigned to HUAWEI TECHNOLOGIES CO., LTD., Shenzhen (CN)
Filed by Amur Ghose, Montreal (CA); Yingxue Zhang, Montreal (CA); and Zhanguang Zhang, Montreal (CA)
Filed on May 28, 2021, as Appl. No. 17/334,657.
Prior Publication US 2022/0405455 A1, Dec. 22, 2022
Int. Cl. G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06N 3/08 (2023.01); G06F 18/20 (2023.01); G06F 18/213 (2023.01); G06F 18/21 (2023.01)
CPC G06F 30/392 (2020.01) [G06F 18/213 (2023.01); G06F 18/2163 (2023.01); G06F 18/29 (2023.01); G06F 30/398 (2020.01); G06N 3/08 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A computer implemented method for assisting electronic chip design, comprising:
receiving netlist data for a proposed electronic chip design, the netlist data including a list of circuit elements and a list of interconnections between the circuit elements;
converting the netlist data to a graph that represents at least some of the circuit elements as nodes and represents the interconnections between the circuit elements as edges;
extracting network embeddings for the nodes based on a graph topology represented by the edges;
extracting degree features for the nodes based on the graph topology; and
computing, using a graph neural network, a respective congestion prediction for each of the circuit elements that are represented as nodes, based on the extracted network embeddings and the extracted degree features.