CPC G06F 30/392 (2020.01) [G06F 18/213 (2023.01); G06F 18/2163 (2023.01); G06F 18/29 (2023.01); G06F 30/398 (2020.01); G06N 3/08 (2013.01)] | 20 Claims |
1. A computer implemented method for assisting electronic chip design, comprising:
receiving netlist data for a proposed electronic chip design, the netlist data including a list of circuit elements and a list of interconnections between the circuit elements;
converting the netlist data to a graph that represents at least some of the circuit elements as nodes and represents the interconnections between the circuit elements as edges;
extracting network embeddings for the nodes based on a graph topology represented by the edges;
extracting degree features for the nodes based on the graph topology; and
computing, using a graph neural network, a respective congestion prediction for each of the circuit elements that are represented as nodes, based on the extracted network embeddings and the extracted degree features.
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