US 11,675,943 B2
Tool to create a reconfigurable interconnect framework
Thomas Boesch, Rovio (CH); and Giuseppe Desoli, San Fermo Della Battaglia (IT)
Assigned to STMICROELECTRONICS S.r.l., Agrate Brianza (IT); and STMICROELECTRONICS INTERNATIONAL N.V., Amsterdam (NL)
Filed by STMICROELECTRONICS S.R.L., Agrate Brianza (IT); and STMICROELECTRONICS INTERNATIONAL N.V., Amsterdam (NL)
Filed on Nov. 10, 2020, as Appl. No. 17/94,743.
Application 16/549,485 is a division of application No. 15/423,292, filed on Feb. 2, 2017, granted, now 10,417,364, issued on Sep. 17, 2019.
Application 17/094,743 is a continuation of application No. 16/549,485, filed on Aug. 23, 2019, granted, now 10,872,186.
Claims priority of application No. 201711000422 (IN), filed on Jan. 4, 2017.
Prior Publication US 2021/0073450 A1, Mar. 11, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 30/327 (2020.01); G06N 20/10 (2019.01); G06N 3/084 (2023.01); G06F 30/34 (2020.01); G06N 20/00 (2019.01); G06N 3/044 (2023.01); G06N 3/045 (2023.01); G06N 3/047 (2023.01); G06N 3/04 (2023.01); G06N 3/08 (2023.01); G06F 115/08 (2020.01); G06N 7/01 (2023.01); G06N 3/063 (2023.01); G06F 9/445 (2018.01); G06F 13/40 (2006.01); G06F 15/78 (2006.01)
CPC G06F 30/327 (2020.01) [G06F 30/34 (2020.01); G06N 3/044 (2023.01); G06N 3/045 (2023.01); G06N 3/047 (2023.01); G06N 3/084 (2013.01); G06N 20/00 (2019.01); G06N 20/10 (2019.01); G06F 9/44505 (2013.01); G06F 13/4022 (2013.01); G06F 15/7817 (2013.01); G06F 2115/08 (2020.01); G06N 3/04 (2013.01); G06N 3/063 (2013.01); G06N 3/08 (2013.01); G06N 7/01 (2023.01)] 26 Claims
OG exemplary drawing
 
1. A non-transitory computer-readable medium storing a configuration template, which, when accessed by a computing device, is used by the computing device to generate a register transfer level (RTL) circuit model of a reconfigurable interconnect framework, the configuration template defining parameters including:
a first number of reconfigurable stream switch output ports of a stream switch of the reconfigurable interconnect framework, the stream switch being arranged to stream data tensors between logical modules, each output port having an output port architectural composition, wherein the output port architectural composition is defined by a plurality of N data paths of the stream switch, the plurality of N data paths including A data outputs and B control outputs, wherein N, A, and B are non-zero integers; and
a second number of reconfigurable stream switch input ports of the stream switch of the reconfigurable interconnect framework, each input port having an input port architectural composition, wherein the input port architectural composition is defined by a plurality of M data paths of the stream switch, the plurality of M data paths including A data inputs and B control inputs.