US 11,675,940 B2
Generating integrated circuit floorplans using neural networks
Chian-Min Richard Ho, Palo Alto, CA (US); William Hang, Stanford, CA (US); Mustafa Nazim Yazgan, Cupertino, CA (US); Anna Darling Goldie, Mountain View, CA (US); Jeffrey Adgate Dean, Palo Alto, CA (US); Azalia Mirhoseini, San Jose, CA (US); Emre Tuncer, Santa Cruz, CA (US); Ya Wang, Foster City, CA (US); and Anand Babu, Palo Alto, CA (US)
Assigned to Google LLC, Mountain View, CA (US)
Filed by Google LLC, Mountain View, CA (US)
Filed on Aug. 23, 2021, as Appl. No. 17/409,566.
Application 17/409,566 is a continuation of application No. 16/889,130, filed on Jun. 1, 2020, granted, now 11,100,266.
Application 16/889,130 is a continuation of application No. 16/703,837, filed on Dec. 4, 2019, granted, now 10,699,043, issued on Jun. 30, 2020.
Claims priority of provisional application 62/775,284, filed on Dec. 4, 2018.
Prior Publication US 2022/0043951 A1, Feb. 10, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 30/27 (2020.01); G06F 30/392 (2020.01)
CPC G06F 30/27 (2020.01) [G06F 30/392 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method performed by one or more computers, the method comprising:
obtaining netlist data for a computer chip, wherein the netlist data specifies a connectivity on a computer chip between a plurality of nodes that each correspond to one or more of a plurality of integrated circuit components of the computer chip;
generating a computer chip floorplan that places each node in the netlist data at a respective position on the surface of the computer chip using a node placement neural network that comprises (i) an input subnetwork configured to, at each of a plurality of time steps, process an input representation for the time step to generate an embedding of the input representation; and (ii) a policy subnetwork configured to, at each of the plurality of time steps, process the embedding of the input representation for the time step to generate a score distribution over a plurality of positions on the surface of the computer chip;
generating, using a reward function that measures a quality of the computer chip floorplan, a reward for the computer chip floorplan; and
training, using at least the reward, at least the policy subnetwork of the node placement neural network through reinforcement learning to generate probability distributions that maximize the reward function.