CPC G06F 13/4027 (2013.01) [G06F 13/4022 (2013.01); G06F 15/17375 (2013.01); G06F 15/17381 (2013.01)] | 22 Claims |
1. A system comprising:
a plurality of processor clusters, where a given processor cluster comprises one or more processors;
a plurality of graphics processing units;
a plurality of memory controllers configured to control access to memory devices;
a plurality of agents; and
a plurality of network switches coupled to the plurality of processor clusters, the plurality of graphics processing units, the plurality of memory controllers, and the plurality of agents, wherein:
a first subset of the plurality of network switches are interconnected to form a central processing unit (CPU) network between the plurality of processor clusters and the plurality of memory controllers,
a second subset of the plurality of network switches are interconnected to form an input/output (I/O) network between the plurality of processor clusters, the plurality of agents, and the plurality of memory controllers,
a third subset of the plurality of network switches are interconnected to form a relaxed order network between the plurality of graphics processing units, selected ones of the plurality of agents, and the plurality of memory controllers,
the CPU network, the I/O network, and the relaxed order network are independent of each other,
the CPU network and the I/O network are coherent, and
the relaxed order network is non-coherent and has reduced ordering constraints compared to the CPU network and I/O network.
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