CPC G06F 13/24 (2013.01) [G06F 9/30101 (2013.01); G06F 9/4812 (2013.01); G06F 9/4818 (2013.01); G06F 9/4831 (2013.01); G06F 13/26 (2013.01); G06F 13/4221 (2013.01)] | 20 Claims |
17. A computing system, comprising:
an interconnect fabric;
a core complex comprising a cluster of processors, the core complex coupled with the interconnect fabric;
a programmable interrupt controller (PIC) coupled to PIC registers comprising arbitration priority registers (APR) and state registers, each APR and state register corresponding to a respective processor of the cluster of processors; and
an input/output hub (I/O hub) coupled to one or more devices and the interconnect fabric, the I/O hub to send an interrupt request from the one or more devices to the PIC over the interconnect fabric, the PIC to select a processor to interrupt from the cluster of processors in the core complex based on the processor residing within a common domain with the I/O hub.
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