US 11,675,718 B2
Enhanced low-priority arbitration
Eric Christopher Morton, Austin, TX (US); Pravesh Gupta, Bengaluru (IN); Bryan P Broussard, Austin, TX (US); and Li Ou, Austin, TX (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Mar. 26, 2021, as Appl. No. 17/214,771.
Prior Publication US 2022/0309013 A1, Sep. 29, 2022
Int. Cl. G06F 13/24 (2006.01); G06F 9/48 (2006.01); G06F 9/30 (2018.01); G06F 13/42 (2006.01); G06F 13/26 (2006.01)
CPC G06F 13/24 (2013.01) [G06F 9/30101 (2013.01); G06F 9/4812 (2013.01); G06F 9/4818 (2013.01); G06F 9/4831 (2013.01); G06F 13/26 (2013.01); G06F 13/4221 (2013.01)] 20 Claims
OG exemplary drawing
 
17. A computing system, comprising:
an interconnect fabric;
a core complex comprising a cluster of processors, the core complex coupled with the interconnect fabric;
a programmable interrupt controller (PIC) coupled to PIC registers comprising arbitration priority registers (APR) and state registers, each APR and state register corresponding to a respective processor of the cluster of processors; and
an input/output hub (I/O hub) coupled to one or more devices and the interconnect fabric, the I/O hub to send an interrupt request from the one or more devices to the PIC over the interconnect fabric, the PIC to select a processor to interrupt from the cluster of processors in the core complex based on the processor residing within a common domain with the I/O hub.