US 11,675,716 B2
Techniques for command bus training to a memory device
Christopher P. Mozak, Portland, OR (US); Steven T. Taylor, Beaverton, OR (US); and Alvin Shing Chye Goh, Bayan Lepas (MY)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 10, 2019, as Appl. No. 16/709,798.
Prior Publication US 2020/0110716 A1, Apr. 9, 2020
Int. Cl. G06F 12/00 (2006.01); G06F 13/16 (2006.01); G06F 13/42 (2006.01); G06F 9/30 (2018.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); H03M 13/09 (2006.01); G06F 18/214 (2023.01)
CPC G06F 13/1689 (2013.01) [G06F 9/30029 (2013.01); G06F 13/4243 (2013.01); G06F 18/214 (2023.01); G11C 7/1045 (2013.01); G11C 7/1048 (2013.01); G11C 7/222 (2013.01); H03M 13/09 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A memory controller comprising:
a command logic to generate a first command to trigger a memory device to enter one of a first command bus training mode or a second command bus training mode to train a command and address (CA) interface of the memory device; and
input/output (I/O) training circuitry to cause a CA pattern to be output via a command bus coupled with the CA interface of the memory device, the I/O training circuitry to also:
compress a sampled CA pattern received from the memory device via a data bus coupled with a DQ interface of the memory device to generate a first compressed value based on the memory device being in the first command bus training mode and forward the first compressed value to the command logic; or
forward, to the command logic, a second compressed value received from the memory device via the data bus, the second compressed value representing the sampled CA pattern compressed at the memory device based on the memory device being in the second command bus training mode.