US 11,675,715 B2
Low pin-count architecture with prioritized message arbitration and delivery
Suresh Sugumar, Singapore (SG); Vishwanath Somayaji, Bangalore (IN); and Sudeep Divakaran, Bangalore (IN)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 27, 2019, as Appl. No. 16/366,789.
Prior Publication US 2019/0236037 A1, Aug. 1, 2019
Int. Cl. G06F 13/16 (2006.01); G06F 1/26 (2006.01); G06F 13/42 (2006.01)
CPC G06F 13/1642 (2013.01) [G06F 1/266 (2013.01); G06F 13/4282 (2013.01); G06F 2213/0042 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A method implemented in a computing device including a processor comprising a first component having a hardware-based message arbitration unit (MAU) including a plurality of priority queues, each having a respective priority level, coupled to a second component via a low-pin count link, comprising:
receiving, at the MAU from two or more clients on the processor, messages having different priority levels to be sent over the low pin-count link to the second component;
enqueuing the messages in the plurality of priority queues based on a priority level for each message; and
arbitrating transmission of messages over the low-pin count link based on the priority level of messages in the plurality of priority queues.