US 11,675,657 B2
Energy-efficient error-correction-detection storage
Frederick A. Ware, Los Altos Hills, CA (US); John E. Linstadt, Palo Alto, CA (US); and Liji Gopalakrishnan, Sunnyvale, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Apr. 15, 2022, as Appl. No. 17/721,735.
Application 17/721,735 is a continuation of application No. 16/832,263, filed on Mar. 27, 2020, granted, now 11,327,831.
Application 16/832,263 is a continuation of application No. 15/963,163, filed on Apr. 26, 2018, granted, now 10,613,924, issued on Apr. 7, 2020.
Claims priority of provisional application 62/507,514, filed on May 17, 2017.
Prior Publication US 2022/0291992 A1, Sep. 15, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/10 (2006.01); G06F 3/06 (2006.01)
CPC G06F 11/1004 (2013.01) [G06F 3/064 (2013.01); G06F 3/0619 (2013.01); G06F 3/0673 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated-circuit (IC) memory buffer comprising:
an external interface to receive external memory requests each specifying a memory address within a range of memory addresses corresponding to a first memory region;
a memory interface to issue successive local memory requests responsive to each of the external memory requests, the successive local memory requests including:
a first local memory request specifying a row address and a first column address within the first memory region;
a second local memory request specifying the row address and a second column address within the first memory region; and
a third local memory request specifying the row address and a third column address corresponding to a second memory region outside of the first memory region.