US 11,675,656 B2
Error detection code generation techniques
Natalija Jovanovic, Munich (DE); and Stefan Dietrich, Türkenfeld (DE)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Feb. 18, 2022, as Appl. No. 17/675,766.
Application 17/675,766 is a continuation of application No. 17/170,462, filed on Feb. 8, 2021, granted, now 11,281,529.
Claims priority of provisional application 62/977,043, filed on Feb. 14, 2020.
Prior Publication US 2022/0171673 A1, Jun. 2, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/00 (2006.01); G06F 11/10 (2006.01)
CPC G06F 11/1004 (2013.01) 20 Claims
OG exemplary drawing
 
1. A method, comprising:
calculating, by a memory device, a first error detection code associated with a first set of bits;
modifying one or more bits of the first set of bits to generate a second set of bits for transmission from the memory device to a host device;
modifying one or more bits of the first error detection code to generate a second error detection code based at least in part on a parity of the modified one or more bits of the first set of bits; and
transmitting, from the memory device to the host device, the second set of bits and the second error detection code.