CPC G06F 11/1004 (2013.01) | 20 Claims |
1. A method, comprising:
calculating, by a memory device, a first error detection code associated with a first set of bits;
modifying one or more bits of the first set of bits to generate a second set of bits for transmission from the memory device to a host device;
modifying one or more bits of the first error detection code to generate a second error detection code based at least in part on a parity of the modified one or more bits of the first set of bits; and
transmitting, from the memory device to the host device, the second set of bits and the second error detection code.
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