US 11,675,645 B2
System and method for tracking memory corrected errors by frequency of occurrence while reducing dynamic memory allocation
David K. Chalfant, Round Rock, TX (US); and Jordan Chin, Austin, TX (US)
Assigned to Dell Products L.P., Round Rock, TX (US)
Filed by DELL PRODUCTS L.P., Round Rock, TX (US)
Filed on Jul. 26, 2021, as Appl. No. 17/385,116.
Application 17/385,116 is a continuation of application No. 16/918,621, filed on Jul. 1, 2020, granted, now 11,138,055.
Prior Publication US 2022/0004451 A1, Jan. 6, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/00 (2006.01); G06F 11/07 (2006.01); G06F 9/50 (2006.01); G06F 11/30 (2006.01); G06F 11/10 (2006.01)
CPC G06F 11/0772 (2013.01) [G06F 9/5016 (2013.01); G06F 11/076 (2013.01); G06F 11/1068 (2013.01); G06F 11/3037 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An information handling system comprising:
a processor to execute an operating system of the information handling system, to detect a corrected error from a memory controller of the information handling system, and to generate a system management interrupt (SMI); and
a basic input/output system (BIOS) to receive the SMI from the processor, and in response to receiving the SMI, to execute an SMI handler, the SMI handler to:
detect a row of the corrected error within a dual inline memory module (DIMM) of the information handling system;
determine whether an entry for the row is located within a hash table; and
in response to the entry for the row being located within the hash table, increment an error count in a field of the entry for the row.