US 11,675,411 B2
Dynamic P2L asynchronous power loss mitigation
Giuseppe D'Eliseo, Caserta (IT); Xiangang Luo, Fremont, CA (US); Ting Luo, Santa Clara, CA (US); and Jianmin Huang, San Carlos, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 9, 2021, as Appl. No. 17/470,506.
Application 17/470,506 is a continuation of application No. 16/406,779, filed on May 8, 2019, granted, now 11,132,044.
Claims priority of provisional application 62/668,733, filed on May 8, 2018.
Prior Publication US 2021/0405726 A1, Dec. 30, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/3206 (2019.01); G06F 12/06 (2006.01); G06F 12/02 (2006.01); G06F 1/3296 (2019.01)
CPC G06F 1/3206 (2013.01) [G06F 1/3296 (2013.01); G06F 12/0246 (2013.01); G06F 12/06 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a storage system comprising control circuitry and a memory array having multiple groups of memory cells,
wherein the control circuitry, when resuming operation from a low-power state, is configured to store a first physical-to-logical (P2L) data structure for a first physical area of a first group of memory cells of the memory array in a block of user data in a second physical area of the first group of memory cells.