US 11,675,326 B2
Method and apparatus for remote field programmable gate array processing
Nicolas A. Salhuana, Tempe, AZ (US); Karthik Kumar, Chandler, AZ (US); Thomas Willhalm, Sandhausen (DE); Francesc Guim Bernat, Barcelona (ES); and Narayan Ranganathan, Bangalore (IN)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on May 26, 2021, as Appl. No. 17/330,738.
Application 17/330,738 is a continuation of application No. 16/314,401, granted, now 11,029,659, previously published as PCT/US2016/040340, filed on Jun. 30, 2016.
Prior Publication US 2021/0294292 A1, Sep. 23, 2021
Int. Cl. G06F 9/06 (2006.01); G05B 19/042 (2006.01); H03K 19/17732 (2020.01); G06F 8/41 (2018.01); H03K 19/17728 (2020.01)
CPC G05B 19/0426 (2013.01) [G06F 8/44 (2013.01); G06F 8/456 (2013.01); H03K 19/17728 (2013.01); H03K 19/17732 (2013.01); G05B 2219/21109 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A network interface controller (NIC), comprising circuitry to:
control access to a network fabric for a local processor;
access data corresponding to respective kernels to program one or more field-programmable gate array (FPGA) accelerators locally communicatively coupled to the local processor; and
receive, via the network fabric, an accelerator programming request, and determine whether a locally-available FPGA accelerator may service the accelerator programming request.