US 11,675,004 B2
Method and apparatus for detecting defective logic devices
Chi-Che Wu, Hsinchu (TW); Tsung-Yang Hung, Hsinchu County (TW); Ming-Yih Wang, Hsin-Chu (TW); and Jia-Ming Guo, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on Aug. 10, 2020, as Appl. No. 16/989,726.
Claims priority of provisional application 63/024,874, filed on May 14, 2020.
Prior Publication US 2021/0356521 A1, Nov. 18, 2021
Int. Cl. G01R 31/3177 (2006.01); G01R 31/30 (2006.01); G01R 31/317 (2006.01)
CPC G01R 31/3177 (2013.01) [G01R 31/3008 (2013.01); G01R 31/31721 (2013.01); G01R 31/31725 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus for testing a device under test (DUT), comprising:
a power supply device configured to provide a first voltage and a second voltage to the DUT;
a clock device; and
a data generating device configured to provide first data to the DUT, wherein
the power supply device is configured to provide the first voltage to the DUT in a first time duration;
the data generating device is configured to provide the first data to the DUT in the first time duration;
the power supply device is configured to provide the second voltage to the DUT in a second time duration after the first time duration;
the clock device is configured to provide a clock signal to the DUT in the first time duration and stop providing the clock signal to the DUT in the second time duration; and
the second voltage is different from the first voltage, wherein the DUT comprises a first number of information storage units connected in series, and the first data comprises a second number of bits, wherein the second number is identical to the first number.