US 11,674,980 B2
Low-profile gimbal platform for high-resolution in situ co-planarity adjustment
Paul J. Diglio, Gaston, OR (US); and Joseph F. Walczyk, Tigard, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Aug. 13, 2020, as Appl. No. 16/992,947.
Application 16/992,947 is a division of application No. 15/721,331, filed on Sep. 29, 2017, granted, now 10,775,414.
Prior Publication US 2020/0371136 A1, Nov. 26, 2020
Int. Cl. G01R 1/073 (2006.01); G01R 1/04 (2006.01); G01R 31/28 (2006.01)
CPC G01R 1/07364 (2013.01) [G01R 1/04 (2013.01); G01R 1/07342 (2013.01); G01R 31/2831 (2013.01); G01R 31/2891 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of operating an integrated circuit (IC) tester platform, the method comprising:
measuring a planar error between a probe card surface and one or more devices under test (DUT);
determining, based on the measuring, which of a plurality of linear actuators in a gimbal platform coupled to a probe card is to operate to reduce the planar error; and
transmitting instructions to cause one or more of the plurality of linear actuators to extend or retract a shaft in a direction non-perpendicular to the probe card surface in a manner that reduces the planar error.