US 11,672,133 B2
Vertically stacked memory elements with air gap
Aaron D. Lilak, Beaverton, OR (US); Patrick R. Morrow, Portland, OR (US); Hui Jae Yoo, Hillsboro, OR (US); Sean T. Ma, Portland, OR (US); Scott B. Clendenning, Portland, OR (US); Abhishek A. Sharma, Hillsboro, OR (US); Ehren Mannebach, Tigard, OR (US); and Urusa Alaan, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 20, 2019, as Appl. No. 16/447,603.
Prior Publication US 2020/0403033 A1, Dec. 24, 2020
Int. Cl. H10B 63/00 (2023.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01)
CPC H10B 63/845 (2023.02) [H01L 21/31116 (2013.01); H01L 21/7682 (2013.01); H10B 41/27 (2023.02); H10B 43/27 (2023.02)] 19 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a vertical layer stack of alternating layers of a conductive material and an insulating material, the stack including an insulating material layer between first and second neighboring conductive material layers; and
an isolation material along a side of the layer stack, the isolation material compositionally distinct from the insulating material;
wherein the insulating material layer has a lateral width that is shorter than a lateral width of the first and second neighboring conductive material layers such that the layer stack defines a void between the first and second neighboring conductive material layers, the void further located between the isolation material and the insulating material.