US 11,672,132 B2
Variable resistance memory device
Tae Hong Ha, Suwon-si (KR); and Jae Rok Kahng, Seoul (KR)
Assigned to Samsung Electronics Co., Ltd.
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jun. 28, 2021, as Appl. No. 17/359,799.
Claims priority of application No. 10-2020-0084603 (KR), filed on Jul. 9, 2020; and application No. 10-2021-0015409 (KR), filed on Feb. 3, 2021.
Prior Publication US 2022/0013581 A1, Jan. 13, 2022
Int. Cl. H10B 63/00 (2023.01); H01L 27/24 (2006.01); H01L 45/00 (2006.01)
CPC H01L 27/249 (2013.01) [H01L 45/1233 (2013.01); H01L 45/06 (2013.01); H01L 45/144 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A variable resistance memory device comprising:
lower conductive lines extending in a first direction on a substrate and spaced apart from each other in a second direction crossing the first direction;
peripheral transistors on the substrate and arranged under the lower conductive lines in a third direction crossing the first direction and the second direction; and
lower contacts electrically connecting the lower conductive lines to the peripheral transistors and extending in the third direction,
wherein each of the lower conductive lines comprises a first lower extending portion extending in the first direction, a second lower extending portion offset in the second direction from the first lower extending portion and extending in the first direction, and a lower connecting portion that couples the first lower extending portion to the second lower extending portion, and
wherein each of the lower contacts is on the lower connecting portion of a respective one of the lower conductive lines.