CPC H01L 27/11582 (2013.01) [G11C 16/08 (2013.01); H01L 21/0214 (2013.01); H01L 27/1157 (2013.01)] | 19 Claims |
1. A memory array, comprising:
a vertical stack of alternating insulative levels and conductive wordlines; the insulative levels having terminal ends comprising first insulative material;
a charge-blocking material extending vertically along the stack;
a charge-storage material being configured as first segments which are arranged one atop another, and which are vertically spaced from one another by intervening second segments comprising the first insulative material within the terminal ends;
a charge-tunneling material adjacent to the charge-storage material; and
a channel material extending vertically along the stack.
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