CPC H04W 72/20 (2023.01) [H04L 1/0026 (2013.01); H04L 1/16 (2013.01); H04L 1/1887 (2013.01); H04L 5/0007 (2013.01); H04W 72/0446 (2013.01); H04W 72/0453 (2013.01); H04W 72/23 (2023.01); H04L 1/1819 (2013.01); H04L 2001/0093 (2013.01)] | 14 Claims |
1. An integrated circuit comprising circuitry configured to control a process of a communication apparatus, wherein the process includes:
receiving control information destined for the communication apparatus in a resource contained in configured resource candidates, the resource being a unit for data allocation in a combination of time and frequency domains, the control information including modulation and coding information of a data packet transmitted on a shared data channel (SDCH) destined for the communication apparatus, wherein a PHY frame of the resource includes a control region and a separate data region, and the control information is located in the data region that is allocated after the control region in the time domain;
monitoring the configured resource candidates, the monitoring including attempting to decode the control information destined for the communication apparatus; and
responsive to the control information being successfully decoded, obtaining the data packet corresponding to the successfully decoded control information.
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