US 11,671,726 B2
Solid-state imaging device
Hiroshi Takahashi, Kanagawa (JP); Ryoichi Nakamura, Kanagawa (JP); and Hidenori Maeda, Kanagawa (JP)
Assigned to SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Filed on Jun. 30, 2022, as Appl. No. 17/854,284.
Application 17/854,284 is a continuation of application No. 16/631,521, granted, now 11,405,569, previously published as PCT/JP2018/023570, filed on Jun. 21, 2018.
Claims priority of application No. 2017-143352 (JP), filed on Jul. 25, 2017; and application No. 2018-088690 (JP), filed on May 2, 2018.
Prior Publication US 2022/0337773 A1, Oct. 20, 2022
Int. Cl. H04N 5/374 (2011.01); H01L 27/146 (2006.01); H04N 5/341 (2011.01)
CPC H04N 5/374 (2013.01) [H01L 27/14621 (2013.01); H01L 27/14627 (2013.01); H01L 27/14643 (2013.01); H04N 5/341 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A solid-state imaging device, comprising:
a first substrate that includes:
a principal surface; and
a pixel portion on the principal surface, wherein the pixel portion includes a plurality of pixels;
a second substrate that includes:
a first surface in contact with the first substrate;
a second surface opposite to the first surface;
an opening in a partial region on the second surface of the second substrate;
at least one sub-chip inside the opening, wherein the at least one sub-chip includes a first circuit configured to execute a first function; and
a first multi-layer wiring layer on the sub-chip and the second substrate, wherein
the first multi-layer wiring layer covers the opening,
the first multi-layer wiring layer includes an external input/output terminal, and
the external input/output terminal overlaps at least one of the second substrate or the at least one sub-chip.