US 11,671,609 B2
DC coefficient signaling at small quantization step sizes
Chih-Lung Lin, Redmond, WA (US); Shankar Regunathan, Redmond, WA (US); and Sridhar Srinivasan, Shanghai (CN)
Assigned to Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed by Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed on Apr. 26, 2022, as Appl. No. 17/729,797.
Application 12/815,029 is a division of application No. 10/893,168, filed on Jul. 17, 2004, granted, now 7,738,554, issued on Jun. 15, 2010.
Application 17/729,797 is a continuation of application No. 17/348,611, filed on Jun. 15, 2021, granted, now 11,575,913.
Application 17/348,611 is a continuation of application No. 16/780,650, filed on Feb. 3, 2020, granted, now 11,070,823, issued on Jul. 20, 2021.
Application 16/780,650 is a continuation of application No. 16/051,094, filed on Jul. 31, 2018, granted, now 10,554,985, issued on Feb. 4, 2020.
Application 16/051,094 is a continuation of application No. 15/068,325, filed on Mar. 11, 2016, granted, now 10,063,863, issued on Aug. 28, 2018.
Application 15/068,325 is a continuation of application No. 12/815,029, filed on Jun. 14, 2010, granted, now 9,313,509, issued on Apr. 12, 2016.
Claims priority of provisional application 60/488,710, filed on Jul. 18, 2003.
Prior Publication US 2022/0256172 A1, Aug. 11, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H04N 19/18 (2014.01); H04N 19/91 (2014.01); H04N 19/70 (2014.01); H04N 19/46 (2014.01); H04N 19/61 (2014.01); H04N 19/124 (2014.01); H04N 19/126 (2014.01); H04N 19/136 (2014.01); H04N 19/137 (2014.01); H04N 19/17 (2014.01); H04N 19/184 (2014.01); H04N 19/186 (2014.01); H04N 19/44 (2014.01); H04N 19/625 (2014.01); H04N 19/176 (2014.01)
CPC H04N 19/18 (2014.11) [H04N 19/124 (2014.11); H04N 19/126 (2014.11); H04N 19/136 (2014.11); H04N 19/137 (2014.11); H04N 19/17 (2014.11); H04N 19/176 (2014.11); H04N 19/184 (2014.11); H04N 19/186 (2014.11); H04N 19/44 (2014.11); H04N 19/46 (2014.11); H04N 19/61 (2014.11); H04N 19/625 (2014.11); H04N 19/70 (2014.11); H04N 19/91 (2014.11)] 20 Claims
OG exemplary drawing
 
1. In a computer system that implements a video decoder, a method comprising:
receiving encoded data in a bit stream for at least part of a video sequence, wherein the encoded data includes, for a given block of a picture of the video sequence:
a first code that indicates a value for a DC differential for a DC coefficient of the given block, wherein the DC differential represents a difference between the DC coefficient and a DC predictor; and
a second code that indicates a refinement of the value for the DC differential, wherein presence of the second code in the bit stream is conditioned on a quantization step size being 1 or 2; and
decoding the encoded data, including, for the given block:
decoding the first code to determine the value for the DC differential;
decoding the second code to determine the refinement;
determining a multiple of the value for the DC differential by multiplying the value for the DC differential by a factor that depends on the quantization step size; and
adding the refinement to the multiple of the value for the DC differential.