CPC H04L 69/28 (2013.01) [H03M 13/25 (2013.01); H03M 13/35 (2013.01); H03M 13/373 (2013.01); H04J 3/067 (2013.01); H04L 63/123 (2013.01); H04Q 9/00 (2013.01); G06F 7/584 (2013.01); H04L 2463/121 (2013.01)] | 27 Claims |
1. A decoder comprising:
a memory to store event reports associated with a number of event intervals, respective event reports comprising event data and Ny bit timing data;
a processor to:
recover an N bit timing data responsive to a number m of Ny bit timing data, wherein Ny is <N; and
determine timing information responsive to the recovered N bit timing data, the timing information represented by linear-feedback-shift-register (LFSR) state information.
|