US 11,671,520 B2
Compact timestamp, encoders and decoders that implement the same, and related devices, systems and methods
Jason M. Sachs, Chandler, AZ (US)
Assigned to Microchip Technology Incorporated, Chandler, AZ (US)
Filed by Microchip Technology Incorporated, Chandler, AZ (US)
Filed on Aug. 2, 2021, as Appl. No. 17/444,248.
Application 17/444,248 is a division of application No. 16/169,501, filed on Oct. 24, 2018, granted, now 11,082,544.
Claims priority of provisional application 62/641,112, filed on Mar. 9, 2018.
Prior Publication US 2021/0368030 A1, Nov. 25, 2021
Int. Cl. H04L 69/28 (2022.01); H04L 9/40 (2022.01); H03M 13/35 (2006.01); H03M 13/37 (2006.01); H03M 13/25 (2006.01); H04J 3/06 (2006.01); H04Q 9/00 (2006.01); G06F 7/58 (2006.01)
CPC H04L 69/28 (2013.01) [H03M 13/25 (2013.01); H03M 13/35 (2013.01); H03M 13/373 (2013.01); H04J 3/067 (2013.01); H04L 63/123 (2013.01); H04Q 9/00 (2013.01); G06F 7/584 (2013.01); H04L 2463/121 (2013.01)] 27 Claims
OG exemplary drawing
 
1. A decoder comprising:
a memory to store event reports associated with a number of event intervals, respective event reports comprising event data and Ny bit timing data;
a processor to:
recover an N bit timing data responsive to a number m of Ny bit timing data, wherein Ny is <N; and
determine timing information responsive to the recovered N bit timing data, the timing information represented by linear-feedback-shift-register (LFSR) state information.