US 11,671,288 B2
Clock data recovery with decision feedback equalization
Ali Hormati, Ecublens Vaud (CH); and Richard Simpson, Bedford (GB)
Assigned to KANDOU LABS, S.A., Lausanne (CH)
Filed by Kandou Labs, S.A., Lausanne (CH)
Filed on Nov. 2, 2021, as Appl. No. 17/517,042.
Application 17/517,042 is a continuation of application No. 17/028,834, filed on Sep. 22, 2020, granted, now 11,165,611.
Application 17/028,834 is a continuation of application No. 16/261,502, filed on Jan. 29, 2019, granted, now 10,785,072, issued on Sep. 22, 2020.
Application 16/261,502 is a continuation of application No. 15/582,545, filed on Apr. 28, 2017, granted, now 10,193,716, issued on Jan. 29, 2019.
Claims priority of provisional application 62/328,716, filed on Apr. 28, 2016.
Prior Publication US 2022/0173943 A1, Jun. 2, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 25/03 (2006.01); H04L 7/00 (2006.01); H04L 7/033 (2006.01)
CPC H04L 25/03949 (2013.01) [H04L 7/0087 (2013.01); H04L 7/033 (2013.01); H04L 25/03057 (2013.01); H04L 25/03885 (2013.01); H04L 7/0025 (2013.01)] 20 Claims
OG exemplary drawing
 
11. An apparatus comprising:
a multi-input comparator (MIC) having four inputs connected to four respective wires of a multiwire bus, the MIC configured to generate a sub-channel output by combining signals received via the four wires, the combining performed according to a sub-channel vector of a plurality of mutually-orthogonal sub-channel vectors;
two samplers, each sampler configured to generate a respective decision by sampling the sub-channel output at a respective speculative decision feedback equalization (DFE) decision threshold of a pair of speculative DFE decision thresholds, each decision generated at a sampling instant determined by a sampling clock;
a data history circuit configured to provide a prior data output;
a data decision selection circuit connected to the data history circuit, the data decision selection circuit configured to output a data decision of the sub-channel output generated by a first sampler of the two samplers according to the prior data output;
a phase-error selection circuit connected to the data history circuit, configured to output an edge trajectory sample of the sub-channel output generated by a second sampler of the two samplers according to the prior data output responsive to a detected data pattern; and
a clock recovery circuit configured to adjust the sampling instant of the sampling clock in response to the phase-error selection circuit.