CPC H04L 25/03949 (2013.01) [H04L 7/0087 (2013.01); H04L 7/033 (2013.01); H04L 25/03057 (2013.01); H04L 25/03885 (2013.01); H04L 7/0025 (2013.01)] | 20 Claims |
11. An apparatus comprising:
a multi-input comparator (MIC) having four inputs connected to four respective wires of a multiwire bus, the MIC configured to generate a sub-channel output by combining signals received via the four wires, the combining performed according to a sub-channel vector of a plurality of mutually-orthogonal sub-channel vectors;
two samplers, each sampler configured to generate a respective decision by sampling the sub-channel output at a respective speculative decision feedback equalization (DFE) decision threshold of a pair of speculative DFE decision thresholds, each decision generated at a sampling instant determined by a sampling clock;
a data history circuit configured to provide a prior data output;
a data decision selection circuit connected to the data history circuit, the data decision selection circuit configured to output a data decision of the sub-channel output generated by a first sampler of the two samplers according to the prior data output;
a phase-error selection circuit connected to the data history circuit, configured to output an edge trajectory sample of the sub-channel output generated by a second sampler of the two samplers according to the prior data output responsive to a detected data pattern; and
a clock recovery circuit configured to adjust the sampling instant of the sampling clock in response to the phase-error selection circuit.
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