US 11,671,238 B2
Secondary phase compensation assist for PLL IO delay
Vivek Sarda, Austin, TX (US)
Assigned to Skyworks Solutions, Inc., Irvine, CA (US)
Filed by Skyworks Solutions, Inc., Irvine, CA (US)
Filed on Aug. 9, 2021, as Appl. No. 17/397,403.
Application 17/397,403 is a continuation of application No. 16/836,706, filed on Mar. 31, 2020, granted, now 11,088,819.
Prior Publication US 2021/0367751 A1, Nov. 25, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 7/00 (2006.01); H04L 7/04 (2006.01)
CPC H04L 7/04 (2013.01) [H04L 7/0037 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A method comprising:
generating a SYNC output signal, the SYNC output signal indicative of indicating when to update a time of day counter;
feeding back the SYNC output signal to an input terminal as a SYNC feedback signal;
determining a time difference between a SYNC input signal and the SYNC feedback signal;
adjusting a timing of the SYNC output signal based on the time difference;
generating a local system clock signal in a phase-locked loop;
generating the SYNC output signal by dividing the local system clock signal;
adjusting a divide value of a divider to adjust the timing of the SYNC output signal based on the time difference; and
determining a residue of the time difference according to a remaining time difference not accounted for by adjusting the divide value.