| CPC H04J 3/0697 (2013.01) [H04L 43/0852 (2013.01)] | 16 Claims |
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13. A computer system for use in association with a data transmission clock signal, a data reception clock signal, and another clock signal, the computer comprising:
a multi-core processor;
solid-state data storage storing instructions for being executed by the multi-core processor; and
a network interface card circuitry comprising:
time counter circuitry to generate time count data for use in association with receive data timestamping and send data timestamping, the receive data timestamping being associated with data reception that is based upon the data reception clock signal, the send data timestamping being associated with data transmission that is based upon the data transmission clock signal;
latency determination circuitry for use in determining, at least in part, signal propagation-related latency data; and
phase difference determining circuitry for use in determining, at least in part, phase difference data, the phase difference data being based upon phase of the another clock signal relative to at least one phase of the data transmission clock signal and/or the data reception clock signal;
wherein:
the signal propagation-related latency data and the phase difference data are for use in adjusting the time count data so as to compensate, at least in part, for at least one potential synchronization difference related to signal propagation latency and/or clock phase difference.
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