CPC H04B 10/70 (2013.01) [G06N 10/00 (2019.01); H04L 7/0087 (2013.01); H04L 7/0091 (2013.01)] | 31 Claims |
1. A quantum controller comprising:
a pulse processor, wherein the pulse processor is operable to generate a first plurality of data in parallel according to one or more responses from a first group of one or more qubits; and
a first transceiver, wherein the first transceiver is operable to:
convert the first plurality of data into a first analog serial data stream,
transmit the first analog serial data stream, over a first communication channel, to a second transceiver,
receive from a third transceiver, via a second communication channel, a second analog serial data stream, and
convert the second analog serial data stream into a second plurality of data wherein the pulse processor is operable to receive the second plurality of data in parallel to control a second group of one or more qubits.
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