CPC H03L 7/0807 (2013.01) [H03L 7/087 (2013.01); H03L 7/0891 (2013.01)] | 18 Claims |
1. A clock recovery circuit comprising:
a first phase-locked loop (PLL) circuit configured to perform a coarse phase fixing operation of controlling a phase of a first reference clock signal, in a training mode, such that a phase difference between the first reference clock signal and a test data signal having a prescribed pattern is located within a dead zone; and
a second PLL circuit configured to perform a fine phase fixing operation on the test data signal, subsequently to the coarse phase fixing operation,
wherein the second PLL circuit is configured to perform a first sampling on the test data signal and perform a first fine phase fixing operation of controlling phases of a plurality of second reference clock signals based on a result of the first sampling, the first sampling being performed by using a first selection reference clock signal having a rising edge closest to a rising edge of the test data signal and a second selection reference clock signal having a falling edge closest to a falling edge of the test data signal among the plurality of second reference clock signals that are sequentially delayed from the first reference clock signal by a unit phase matching a unit interval of the test data signal, the phase of the first reference clock signal being controlled through the coarse phase fixing operation, in the training mode.
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