US 11,671,104 B2
Clock recovery circuit, clock data recovery circuit, and apparatus including the same
Geumyoung Tak, Seoul (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Dec. 20, 2021, as Appl. No. 17/556,007.
Application 17/556,007 is a continuation of application No. 17/015,437, filed on Sep. 9, 2020, granted, now 11,233,518.
Claims priority of application No. 10-2019-0167143 (KR), filed on Dec. 13, 2019.
Prior Publication US 2022/0116047 A1, Apr. 14, 2022
Int. Cl. H03D 3/24 (2006.01); H03L 7/08 (2006.01); H03L 7/089 (2006.01); H03L 7/087 (2006.01)
CPC H03L 7/0807 (2013.01) [H03L 7/087 (2013.01); H03L 7/0891 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A clock recovery circuit comprising:
a first phase-locked loop (PLL) circuit configured to perform a coarse phase fixing operation of controlling a phase of a first reference clock signal, in a training mode, such that a phase difference between the first reference clock signal and a test data signal having a prescribed pattern is located within a dead zone; and
a second PLL circuit configured to perform a fine phase fixing operation on the test data signal, subsequently to the coarse phase fixing operation,
wherein the second PLL circuit is configured to perform a first sampling on the test data signal and perform a first fine phase fixing operation of controlling phases of a plurality of second reference clock signals based on a result of the first sampling, the first sampling being performed by using a first selection reference clock signal having a rising edge closest to a rising edge of the test data signal and a second selection reference clock signal having a falling edge closest to a falling edge of the test data signal among the plurality of second reference clock signals that are sequentially delayed from the first reference clock signal by a unit phase matching a unit interval of the test data signal, the phase of the first reference clock signal being controlled through the coarse phase fixing operation, in the training mode.