US 11,671,086 B2
Circuit system
Yuya Kimura, Kanagawa (JP); Hisashi Owa, Kanagawa (JP); and Takashi Nakamura, Tokyo (JP)
Assigned to Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Appl. No. 17/603,413
Filed by Sony Semiconductor Solutions Corporation, Kanagawa (JP)
PCT Filed Apr. 3, 2020, PCT No. PCT/JP2020/015277
§ 371(c)(1), (2) Date Oct. 13, 2021,
PCT Pub. No. WO2020/241048, PCT Pub. Date Dec. 3, 2020.
Claims priority of application No. JP2019-098134 (JP), filed on May 24, 2019.
Prior Publication US 2022/0216860 A1, Jul. 7, 2022
Int. Cl. H03K 5/156 (2006.01); H03K 5/13 (2014.01); H03K 19/20 (2006.01); H03K 5/00 (2006.01)
CPC H03K 5/1565 (2013.01) [H03K 5/13 (2013.01); H03K 19/20 (2013.01); H03K 2005/00019 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit system comprising:
a clock tree circuit that has multiple lanes to which a clock signal is distributed;
a duty correction circuit that is provided on each of the multiple lanes and corrects a duty ratio of the clock signal;
a clock gating circuit group having a clock gating circuit that is provided on each of the multiple lanes and receives, as input, the clock signal from the duty correction circuit, the clock gating circuit group starting output of the clock signal from each of a plurality of the clock gating circuits in a predetermined period; and
a variable delay circuit that is provided in association with each of a plurality of the duty correction circuits and is capable of changing a delay time of a control signal that controls a timing of starting output of the clock signal from the clock gating circuit.