US 11,671,078 B2
Clock signal generation
Bruno Gailhard, Peypin (FR)
Assigned to STMicroelectronics (Rousset) SAS, Rousset (FR)
Filed by STMicroelectronics (Rousset) SAS, Rousset (FR)
Filed on Nov. 5, 2021, as Appl. No. 17/520,063.
Claims priority of application No. 2011735 (FR), filed on Nov. 16, 2020.
Prior Publication US 2022/0158628 A1, May 19, 2022
Int. Cl. H03K 3/03 (2006.01); H03K 5/26 (2006.01); H03L 7/093 (2006.01); H03L 7/099 (2006.01); G06F 1/06 (2006.01); G06F 1/08 (2006.01); H03K 5/00 (2006.01)
CPC H03K 3/0315 (2013.01) [G06F 1/06 (2013.01); G06F 1/08 (2013.01); H03K 5/00006 (2013.01); H03K 5/26 (2013.01); H03L 7/093 (2013.01); H03L 7/0995 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device for generating a plurality of first clock signals, the device comprising:
a plurality of first circuits, each of the first circuits including a ring oscillator configured to deliver one of the plurality of first clock signals, the ring oscillator being coupled to a first node configured to receive a first current, each of the first circuits including:
a first current source configured to supply the first current to the first node;
a second node coupled to the first node;
a second circuit configured to supply, to the second node, a second current determined by the second signal; and
a third circuit configured to draw a third current from the second node;
a signal selection circuit configured to receive the first clock signals and to deliver a first clock signal selected from among the first clock signals; and
a phase-locked loop configured to deliver a second signal varying according to a difference between a frequency of the first selected clock signal and a set point frequency determined by a frequency of a third signal which is a clock signal received by the phase-locked loop.