US 11,671,076 B2
Duty cycle detection circuit and duty cycle correction circuit including the same
Dae Ho Yang, Icheon-si (KR); Kwan Su Shon, Icheon-si (KR); Yo Han Jeong, Icheon-si (KR); and Dong Shin Jo, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Nov. 2, 2022, as Appl. No. 17/979,583.
Application 17/979,583 is a division of application No. 17/229,348, filed on Apr. 13, 2021, granted, now 11,522,529.
Claims priority of application No. 10-2020-0185905 (KR), filed on Dec. 29, 2020.
Prior Publication US 2023/0046522 A1, Feb. 16, 2023
Int. Cl. H03K 3/017 (2006.01); G11C 7/22 (2006.01)
CPC H03K 3/017 (2013.01) [G11C 7/222 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A duty cycle correction circuit comprising:
a duty adjustment unit configured to output signals, which are obtained by adjusting a duty of differential clock signals according to duty detection signals, as duty-adjusted differential clock signals; and
a duty cycle detection circuit configured to compare current duty detection signals and previous duty detection signals, which are generated by a first combination and a second combination of the duty-adjusted differential clock signals inputted to a first input terminal and a second input terminal thereof at a time difference, and to adjust an offset of at least one of the first input terminal and the second input terminal.