CPC H03K 3/017 (2013.01) [G11C 7/222 (2013.01)] | 7 Claims |
1. A duty cycle correction circuit comprising:
a duty adjustment unit configured to output signals, which are obtained by adjusting a duty of differential clock signals according to duty detection signals, as duty-adjusted differential clock signals; and
a duty cycle detection circuit configured to compare current duty detection signals and previous duty detection signals, which are generated by a first combination and a second combination of the duty-adjusted differential clock signals inputted to a first input terminal and a second input terminal thereof at a time difference, and to adjust an offset of at least one of the first input terminal and the second input terminal.
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