US 11,671,013 B2
Control logic performance optimizations for universal serial bus power delivery controller
Arun Khamesra, Bangalore (IN); Hariom Rai, Bangalore (IN); Rajesh Karri, Visakhapatnam (IN); and Pulkit Shah, Bangalore (IN)
Assigned to Cypress Semiconductor Corporation, San Jose, CA (US)
Filed by Cypress Semiconductor Corporation, San Jose, CA (US)
Filed on Aug. 31, 2021, as Appl. No. 17/463,339.
Claims priority of provisional application 63/074,635, filed on Sep. 4, 2020.
Claims priority of provisional application 63/073,866, filed on Sep. 2, 2020.
Prior Publication US 2022/0069713 A1, Mar. 3, 2022
Int. Cl. H02M 3/158 (2006.01); H03F 3/45 (2006.01)
CPC H02M 3/1582 (2013.01) [H03F 3/45475 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) controller for a Universal Serial Bus (USB) Type-C device, the IC controller comprising:
an error amplifier (EA) coupled between an output and an input of the IC controller, the EA comprising:
an EA output coupled to a pulse width modulation (PWM) comparator of a buck-boost converter;
a first transconductance amplifier to adjust a current at the EA output, wherein the first transconductance amplifier operates in a constant voltage mode; and
a second transconductance amplifier to adjust the current at the EA output, wherein the second transconductance amplifier operates in a constant current mode;
a first set of programmable registers coupled to the first transconductance amplifier to store a first set of increasingly higher transconductance values;
a second set of programmable registers coupled to the second transconductance amplifier to store a second set of increasingly higher transconductance values; and
control logic operatively coupled to the EA, the control logic to:
cause the first transconductance amplifier to operate while sequentially using transconductance values stored in at least two of the first set of programmable registers; and
cause the second transconductance amplifier to operate while sequentially using transconductance values stored in at least two of the second set of programmable registers.