US 11,671,010 B2
Power delivery for multi-chip-package using in-package voltage regulator
Alan Roth, Leander, TX (US); Haohua Zhou, Fremont, CA (US); Eric Soenen, Austin, TX (US); Ying-Chih Hsu, Hsin-Chu (TW); Paul Ranucci, Leander, TX (US); Mei Hsu Wong, Saratoga, CA (US); and Tze-Chiang Huang, Saratoga, CA (US)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Aug. 12, 2020, as Appl. No. 16/991,335.
Claims priority of provisional application 62/971,693, filed on Feb. 7, 2020.
Prior Publication US 2021/0249952 A1, Aug. 12, 2021
Int. Cl. H02M 3/156 (2006.01); H01L 23/498 (2006.01); H01L 23/58 (2006.01); H01L 23/495 (2006.01)
CPC H02M 3/156 (2013.01) [H01L 23/49589 (2013.01); H01L 23/49811 (2013.01); H01L 23/49838 (2013.01); H01L 23/58 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a first substrate including a first surface and a second surface opposite to the first surface;
a first die disposed over the second surface of the first substrate;
a second die disposed over the second surface of the first substrate and adjacent to the first die;
a plurality of first conductive bumps disposed between the first substrate and the first die and between the first substrate and the second die;
a second substrate disposed below the first surface of the first substrate;
a plurality of second conductive bumps disposed between the first substrate and the second substrate;
an in-package voltage regulator (PVR) chip disposed over the second substrate;
a molding material disposed over the first substrate and surrounding the first die, the second die, the plurality of first conductive bumps, the plurality of second conductive bumps, and the PVR chip; and
an integrated passive die (IPD) chip comprising a capacitive device disposed in one or more trenches in a semiconductor substrate of the IPD chip, the semiconductor substrate of the IPD chip being arranged between the first substrate and the second substrate and being laterally surrounded by the plurality of second conductive bumps.