US 11,670,714 B2
Negative differential resistance device
Kilsu Jung, Suwon-si (KR); Jin-Hong Park, Hwaseong-si (KR); Keun Heo, Yongin-si (KR); and Sungjun Kim, Incheon (KR)
Assigned to Samsung Electronics Co., Ltd.; and Research & Business Foundation Sungkyunkwan University
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jun. 3, 2021, as Appl. No. 17/338,400.
Claims priority of application No. 10-2020-0122860 (KR), filed on Sep. 23, 2020.
Prior Publication US 2022/0093803 A1, Mar. 24, 2022
Int. Cl. H01L 29/78 (2006.01); H01L 29/267 (2006.01); H01L 29/51 (2006.01); H01L 29/76 (2006.01); H01L 29/45 (2006.01); H10K 10/84 (2023.01); H10K 10/46 (2023.01)
CPC H01L 29/78391 (2014.09) [H01L 29/267 (2013.01); H01L 29/45 (2013.01); H01L 29/516 (2013.01); H01L 29/7606 (2013.01); H10K 10/466 (2023.02); H10K 10/472 (2023.02); H10K 10/84 (2023.02)] 18 Claims
OG exemplary drawing
 
1. A negative differential resistance device, comprising:
a conductive substrate;
a dielectric layer comprising a first surface and a second surface opposing the first surface;
a first semiconductor layer comprising a first degenerated layer that is on the first surface of the dielectric layer and has a first polarity;
a second semiconductor layer comprising a second degenerated layer that comprises a region that overlaps the first semiconductor layer and has a second polarity;
a first electrode electrically connected to the first semiconductor layer;
a second electrode electrically connected to the second semiconductor layer;
a third electrode between the second surface of the dielectric layer and the conductive substrate, wherein the third electrode overlaps both the first semiconductor layer and the second semiconductor layer; and
an insulating layer between the second surface of the dielectric layer and the conductive substrate, in a region not overlapping the third electrode in a direction perpendicular to the second surface of the dielectric layer,
wherein the insulating layer does not overlap the third electrode in a region that overlaps both the first semiconductor layer and the second semiconductor layer.