US 11,670,700 B2
Semiconductor device
Young-Kwan Kim, Daejeon (KR); Hyuck Joon Kwon, Yongin-si (KR); and Jae Beom Jeon, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Mar. 24, 2021, as Appl. No. 17/211,469.
Claims priority of application No. 10-2020-0094189 (KR), filed on Jul. 29, 2020.
Prior Publication US 2022/0037508 A1, Feb. 3, 2022
Int. Cl. H01L 29/66 (2006.01); H01L 23/544 (2006.01); H10B 12/00 (2023.01); H10B 10/00 (2023.01); H01L 29/423 (2006.01); H01L 27/108 (2006.01); H01L 27/11 (2006.01); H10B 41/50 (2023.01); H01L 27/11548 (2017.01)
CPC H01L 29/66545 (2013.01) [H01L 23/544 (2013.01); H01L 27/10823 (2013.01); H01L 27/10876 (2013.01); H01L 27/10894 (2013.01); H01L 27/10897 (2013.01); H01L 27/1116 (2013.01); H01L 29/4236 (2013.01); H01L 27/11548 (2013.01); H01L 2223/5446 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory element comprising:
a substrate including a memory cell region and a peripheral circuit region;
an active region located in the memory cell region;
a gate pattern buried in the active region and including a gate electrode;
a conductive line disposed above the gate pattern;
a first region including a plurality of peripheral elements placed in the peripheral circuit region;
a dummy pattern buried in the peripheral circuit region;
a second region which includes the dummy pattern and does not overlap the first region; and
a conductive via disposed on the gate electrode, and connected to the gate electrode and the conductive line.