US 11,670,655 B2
Edge seals for semiconductor packages
Jeffrey Peter Gambino, Gresham, OR (US); Kyle Thomas, San Francisco, CA (US); David T. Price, Gresham, OR (US); Rusty Winzenread, San Jose, CA (US); and Bruce Greenwood, Gresham, OR (US)
Assigned to SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Scottsdale, AZ (US)
Filed by SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Phoenix, AZ (US)
Filed on Aug. 9, 2019, as Appl. No. 16/537,149.
Application 16/537,149 is a division of application No. 15/421,505, filed on Feb. 1, 2017, granted, now 10,431,614.
Prior Publication US 2019/0363124 A1, Nov. 28, 2019
Int. Cl. H01L 27/146 (2006.01)
CPC H01L 27/14618 (2013.01) [H01L 27/14634 (2013.01); H01L 27/14636 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a digital signal processor comprising a first side and a second side;
an image sensor array comprising a first side and a second side, the first side of the image sensor array coupled to the second side of the digital signal processor through a plurality of hybrid bond interconnect (HBI) bond pads and a first edge seal coupled directly with the plurality of HBI bond pads;
an etch stop layer comprised in the second side of the digital signal processor;
one or more first openings extending from the second side of the image sensor array into the second side of the digital signal processor and to the etch stop layer in the second side of the digital signal processor, the one or more first openings coated with sealing material, the one or more first openings forming a second edge seal between the plurality of HBI bond pads and an edge of the digital signal processor;
one or more second openings extending from the second side of the image sensor array to a second metal stack comprised in the image sensor, the one or more second openings forming a third edge seal wherein the one or more second openings each comprise sealing material therein; and
one or more third openings extending from the second side of the image sensor array to the etch stop layer in the digital signal processor forming a fourth edge seal wherein the one or more third openings may be positioned one of inside and outside the first edge seal;
wherein the first edge seal is comprised of a first metal stack comprised within the digital signal processor directly coupled to the second metal stack comprised within the image sensor array.