US 11,670,623 B2
Semiconductor package
Myung Sam Kang, Hwaseong-si (KR); Sang Kyu Lee, Suwon-si (KR); Jin Gu Kim, Suwon-si (KR); and Yong Koon Lee, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jan. 22, 2021, as Appl. No. 17/155,260.
Claims priority of application No. 10-2020-0081878 (KR), filed on Jul. 3, 2020.
Prior Publication US 2022/0005793 A1, Jan. 6, 2022
Int. Cl. H01L 25/10 (2006.01); H01L 25/00 (2006.01)
CPC H01L 25/105 (2013.01) [H01L 25/50 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1041 (2013.01); H01L 2225/1058 (2013.01); H01L 2225/1094 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a first substrate;
a mold layer provided on the first substrate;
a first semiconductor chip provided on the first substrate;
a heat sink structure comprising a heat sink pattern provided on the first semiconductor chip, a metal film pattern provided on the heat sink pattern, and an insulating film provided on side walls of the heat sink pattern and side walls of the metal film pattern;
an interposer provided on the heat sink structure; and
a solder ball provided to the heat sink structure and the interposer,
wherein the mold layer is provided to surround the insulating film.