US 11,670,620 B2
Device with embedded high-bandwidth, high-capacity memory using wafer bonding
Khandker Nazrul Quader, Santa Clara, CA (US); Robert Norman, Pendleton, OR (US); Frank Sai-keung Lee, San Jose, CA (US); Christopher J. Petti, Mountain View, CA (US); Scott Brad Herner, Lafayette, CO (US); Siu Lung Chan, San Jose, CA (US); Sayeef Salahuddin, Walnut Creek, CA (US); Mehrdad Mofidi, Los Altos Hills, CA (US); and Eli Harari, Saratoga, CA (US)
Assigned to SUNRISE MEMORY CORPORATION, San Jose, CA (US)
Filed by Sunrise Memory Corporation, Fremont, CA (US)
Filed on Jan. 29, 2020, as Appl. No. 16/776,279.
Claims priority of provisional application 62/843,733, filed on May 6, 2019.
Claims priority of provisional application 62/803,689, filed on Feb. 11, 2019.
Claims priority of provisional application 62/798,673, filed on Jan. 30, 2019.
Prior Publication US 2020/0243486 A1, Jul. 30, 2020
Int. Cl. H01L 25/065 (2023.01); H01L 25/00 (2006.01); G06N 3/02 (2006.01); G06F 3/06 (2006.01); G06F 11/10 (2006.01); G06F 12/0802 (2016.01); G11C 16/04 (2006.01)
CPC H01L 25/0657 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0655 (2013.01); G06F 3/0679 (2013.01); G06F 11/1068 (2013.01); G06F 12/0802 (2013.01); G06N 3/02 (2013.01); H01L 25/50 (2013.01); G06F 2212/60 (2013.01); G06F 2212/72 (2013.01); G11C 16/0483 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01)] 61 Claims
OG exemplary drawing
 
1. An electronic device, comprising:
a memory circuit fabricated on a first semiconductor die, wherein the memory circuit comprises a quasi-volatile memory circuit that includes a plurality of modular memory units, each modular memory unit comprising (i) a three-dimensional array of storage transistors organized into a plurality of memory strings; and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and
a logic circuit fabricated on a second semiconductor die, wherein the logic circuit includes a plurality of conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die.