CPC H01L 23/5283 (2013.01) [H01L 21/76814 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 27/11548 (2013.01); H01L 27/11551 (2013.01); H01L 27/11575 (2013.01); H01L 27/11578 (2013.01)] | 20 Claims |
1. A three-dimensional (3D) memory device, comprising:
a memory array structure; and
a staircase structure in an intermediate of the memory array structure and laterally dividing the memory array structure into a first memory array structure and a second memory array structure, the staircase structure comprising a first staircase zone and a bridge structure connecting the first memory array structure and the second memory array structure, and the first staircase zone being at one side of the bridge structure,
wherein
the first staircase zone comprises a first pair of staircases, the first pair of staircase comprising a first staircase and a second staircase arranged and facing each other in a first lateral direction, the first staircase being adjacent to the second staircase in the first lateral direction;
in a second lateral direction perpendicular to the first lateral direction, the first pair of staircases comprises a plurality of divisions at different depths, and in each division of the divisions, each staircase comprises a plurality of stairs at different depths in the first lateral direction and each stair in the first staircase corresponds to, in the first lateral direction, a stair in the second staircase at a same level;
in a first division of the plurality of divisions, a depth of a first stair in the first staircase is different from a depth of a second stair, at a corresponding level, in the second staircase;
the bridge structure comprises a same depth along the first lateral direction; and
at least one stair in the first pair of staircases is electrically connected to at least one of the first memory array structure or the second memory array structure through the bridge structure.
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