US 11,670,573 B2
Low-stress passivation layer
Hsiang-Ku Shen, Hsinchu (TW); Chun-Li Lin, Hsinchu (TW); and Dian-Hau Chen, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jun. 3, 2021, as Appl. No. 17/337,965.
Application 17/337,965 is a division of application No. 16/656,617, filed on Oct. 18, 2019, granted, now 11,031,325.
Prior Publication US 2021/0287973 A1, Sep. 16, 2021
Int. Cl. H01L 23/495 (2006.01); H01L 23/498 (2006.01); H01L 23/532 (2006.01); H01L 21/48 (2006.01); H01L 21/02 (2006.01)
CPC H01L 23/49811 (2013.01) [H01L 21/02274 (2013.01); H01L 21/486 (2013.01); H01L 23/53219 (2013.01); H01L 23/53233 (2013.01); H01L 23/53295 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a redistribution layer comprising:
a passivation layer, and
a first conductive feature and a second conductive feature disposed in the passivation layer;
a first contact feature disposed over and electrically coupled to the first conductive feature;
a second contact feature disposed over and electrically coupled to the second conductive feature; and
a passivation feature extending from between the first conductive feature and the second conductive feature to between the first contact feature and the second contact feature, the passivation feature comprising:
a dielectric feature including a planar top surface extending from a first end of the passivation feature adjacent the first contact feature to a second end of the passivation feature adjacent the second contact feature, and
a dielectric layer disposed on the planar top surface of the dielectric feature,
wherein a composition of the dielectric feature is different from a composition of the dielectric layer,
wherein the passivation feature partially extends into the passivation layer.