US 11,670,565 B2
Semiconductor package with heat dissipation member
Hyo-Chang Ryu, Cheonan-si (KR); Chulwoo Kim, Incheon (KR); Juhyun Lyu, Cheonan-si (KR); Sanghyun Lee, Cheonan-si (KR); and Yun Seok Choi, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on May 4, 2021, as Appl. No. 17/307,181.
Claims priority of application No. 10-2020-0067277 (KR), filed on Jun. 3, 2020.
Prior Publication US 2021/0384100 A1, Dec. 9, 2021
Int. Cl. H01L 23/367 (2006.01); H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01)
CPC H01L 23/3675 (2013.01) [H01L 24/32 (2013.01); H01L 25/0655 (2013.01); H01L 23/367 (2013.01); H01L 25/50 (2013.01); H01L 2224/32237 (2013.01); H01L 2924/3511 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a first substrate;
a first chip structure and a second chip structure spaced apart from each other on the first substrate, a gap region being defined between the first and second chip structures; and
a heat dissipation member covering the first chip structure, the second chip structure, and the first substrate, the heat dissipation member including a first trench in an inner top surface of the heat dissipation member,
wherein the first trench vertically overlaps with the gap region, a width between directly facing inner sidewalls of the first trench being greater than a width of the gap region, and
wherein the first trench vertically overlaps with at least a portion of a top surface of the first chip structure or a portion of a top surface of the second chip structure.