US 11,670,555 B2
PCM metal shielding for wafer testing
Jacob Hamilton, San Diego, CA (US); Tran Kononova, San Diego, CA (US); Jay Kothari, San Diego, CA (US); Matt Allison, Oceanside, CA (US); Kim T. Nguyen, San Diego, CA (US); and Eric S. Shapiro, San Diego, CA (US)
Assigned to PSEMI CORPORATION, San Diego, CA (US)
Filed by pSemi Corporation, San Diego, CA (US)
Filed on Dec. 18, 2020, as Appl. No. 17/127,884.
Prior Publication US 2022/0199475 A1, Jun. 23, 2022
Int. Cl. H01L 21/66 (2006.01); H01L 23/00 (2006.01); G01R 31/28 (2006.01); H01L 23/58 (2006.01)
CPC H01L 22/32 (2013.01) [G01R 31/2884 (2013.01); H01L 23/562 (2013.01); H01L 23/564 (2013.01); H01L 23/585 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A wafer comprising a plurality of dies including a first die and a second die adjacent to or in proximity of the first die, wherein:
the first die comprises a device under test configured to receive radio frequency (RF) test signals through a wafer probe for wafer testing, the wafer probe including traces to conduct the RF test signals; and
the second die comprises test pads, circuits and a patterned metal layer patterned to electrically shield the traces conducting the RF test signals applied to the first die from the circuits in the second die, the test pads being electrically isolated from the patterned metal layer.