US 11,670,548 B2
Structure and method for fabricating a computing system with an integrated voltage regulator module
Vidhya Ramachandran, Cupertino, CA (US); Jun Zhai, San Jose, CA (US); Chonghua Zhong, Cupertino, CA (US); Kunzhong Hu, Cupertino, CA (US); Shawn Searles, Austin, TX (US); Joseph T. DiBene, II, Corralitos, CA (US); and Mengzhi Pang, Cupertino, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Oct. 26, 2020, as Appl. No. 17/80,609.
Application 17/080,609 is a continuation of application No. 15/943,673, filed on Apr. 2, 2018, granted, now 10,818,632.
Application 15/943,673 is a continuation of application No. 15/264,087, filed on Sep. 13, 2016, granted, now 9,935,076, issued on Apr. 3, 2018.
Claims priority of provisional application 62/234,776, filed on Sep. 30, 2015.
Prior Publication US 2021/0043511 A1, Feb. 11, 2021
Int. Cl. H01L 21/77 (2017.01); H01L 25/16 (2023.01); H01L 25/03 (2006.01); H01L 25/18 (2023.01); H01L 21/66 (2006.01); H01L 23/00 (2006.01)
CPC H01L 21/77 (2013.01) [H01L 22/20 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 25/03 (2013.01); H01L 25/16 (2013.01); H01L 25/18 (2013.01); H01L 24/17 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/1403 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/16265 (2013.01); H01L 2224/1703 (2013.01); H01L 2224/17181 (2013.01); H01L 2224/24195 (2013.01); H01L 2924/12 (2013.01); H01L 2924/1205 (2013.01); H01L 2924/1206 (2013.01); H01L 2924/1427 (2013.01); H01L 2924/1432 (2013.01); H01L 2924/1433 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/15192 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/18161 (2013.01); H01L 2924/18162 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19042 (2013.01); H01L 2924/19103 (2013.01); H01L 2924/19104 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a system-on-a-chip integrated circuit included in a first layer of a system package including a first plurality of conductive paths;
a voltage regulator integrated circuit included in a second layer of the system package, wherein the voltage regulator integrated circuit includes an output terminal that is coupled to an input terminal of the system-on-a-chip integrated circuit using a first subset of the first plurality of conductive paths, wherein the voltage regulator integrated circuit is configured to generate a regulated power supply voltage on the output terminal;
a plurality of passive element integrated circuits included in the second layer of the system package, wherein a given passive element integrated circuit of the plurality of passive element integrated circuits is coupled to the voltage regulator integrated circuit using a second subset of the first plurality of conductive paths; and
an interconnect region included in a third layer of the system package, wherein the interconnect region includes a second plurality of conductive paths and is coupled to a first plurality of solder balls.