US 11,670,546 B2
Semiconductor structure and manufacturing method thereof
Yu-Kai Lin, Changhua County (TW); Su-Jen Sung, Hsinchu County (TW); Tze-Liang Lee, Hsinchu (TW); and Jen-Hung Wang, Hsinchu County (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Mar. 4, 2021, as Appl. No. 17/192,805.
Prior Publication US 2022/0285210 A1, Sep. 8, 2022
Int. Cl. H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01); H01L 21/311 (2006.01)
CPC H01L 21/76832 (2013.01) [H01L 21/31116 (2013.01); H01L 21/31144 (2013.01); H01L 21/76802 (2013.01); H01L 21/76826 (2013.01); H01L 21/76828 (2013.01); H01L 21/76843 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 23/53238 (2013.01)] 20 Claims
OG exemplary drawing
 
8. A semiconductor structure, comprising:
a substrate; and
an interconnect structure disposed over the substrate, the interconnect structure comprising interlayer dielectric layers, an etch stop layer between two of the interlayer dielectric layers and conductive features embedded in the interlayer dielectric layers, wherein the etch stop layer comprises an insulating layer and a silicon-containing insulating layer over the insulating layer, the insulating layer comprises a metal oxide region covering at least one of the interlayer dielectric layers and at least one metal nitride region covering the conductive features.