CPC H01L 21/743 (2013.01) | 20 Claims |
1. A 3D device comprising:
a first level, said first level comprising a first single crystal layer;
control circuitry disposed in and/or on said first level,
wherein said control circuitry comprises first single crystal transistors;
a first metal layer disposed above said first single crystal layer;
a second metal layer disposed above said first metal layer;
a third metal layer disposed above said second metal layer;
at least one second level disposed on top of or above said third metal layer;
wherein said at least one second level comprises a plurality of second transistors;
a fourth metal layer disposed above said at least one second level;
a fifth metal layer disposed above said fourth metal layer,
wherein said at least one second level comprises at least one first oxide layer overlaid by a transistor layer and then overlaid by a second oxide layer,
wherein a distance from a top of said first oxide layer to a bottom of said second oxide layer is less than two microns; and
a global power distribution grid,
wherein said global power distribution grid comprises said fifth metal layer; and
a local power distribution grid,
wherein said local power distribution grid comprises said second metal layer, and
wherein a first typical thickness of said fifth metal layer is at least 50% greater than a second typical thickness of said second metal layer.
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